42455-AC10
Synthesis and Characterization of High Density Semiconductor Nanowire Arrays
Silicon nanowire (SiNW) arrays are of interest for applications in photovoltaics and photoelectrochemistry.� High density SiNW arrays offer several potential advantages for solar cell applications in terms of fabrication costs and conversion efficiency.� The development of nanowire-based devices has been limited, however, due in part, to a lack of understanding of the basic electrical properties of SiNWs and nanowire array structures.�
Our studies in this area have been focused on fabricating and characterizing the electrical properties of high density SiNW arrays.� The nanowires were synthesized using a vapor-liquid-solid (VLS) mechanism, in which gold serves as the catalyst for axial wire growth from a Si-containing precursor gas.� Our initial work in the project focused on VLS growth of SiNWs in nanoporous anodized alumina (AAO) membranes.� The AAO membranes provide a support structure for nanowire growth and enable the fabrication of top and bottom contacts to the nanowires for electrical characterization. Using this approach, we demonstrated the fabrication of p-type and n-type Si nanowire arrays and measured the resistivity of the wires as a function of the dopant concentration in the inlet gas during growth.� During the past year, we extended this work to demonstrate the fabrication of radial p-n junction silicon nanowire arrays on AAO-templated glass substrates.� The substrates, supplied by Illuminex Corp., were prepared by anodization of an aluminum film deposited on indium tin oxide (ITO)-coated glass to form a thin (~2 micron) AAO membrane with an average pore diameter of ~100 nm.� A small segment of gold was electrodeposited at the base of the pores, in direct contact with the ITO, to serve as the metal catalyst for nanowire growth.� SiNW growth was carried out in a low pressure chemical vapor deposition system using SiH4 as the source gas and trimethylboron and phosphine as p-type and n-type dopant sources, respectively.� A 1 micron long highly doped (p+) nanowire segment was grown first in order to minimize the contact resistance to the ITO layer.� This was followed by growth of ~25 micron long lightly doped p-SiNWs.� The p-type SiNWs were then uniformly coated with a thin highly doped n-type Si shell layer.� Prior to the shell layer deposition, the gold tips were etched off the SiNWs to prevent the Au from diffusing and causing further nanowire nucleation.� In this structure, the AAO template serves to isolate the n-type Si layer from contacting the backside ITO layer.� Structural characterization of the SiNWs by transmission electron microscopy revealed that the p-type SiNW cores are single crystal with an average diameter of 80 nm +/- 20 nm while the n-type shell layer was polycrystalline with an average thickness of ~40 nm. A thin layer of aluminum was sputter deposited on the top surface of the sample to serve as an electrical contact to the n-type Si shell layer. Initial current-voltage measurements carried out on the radial p-n SiNW arrays on glass revealed rectifying behavior although the diodes exhibited a large reverse leakage current and high ideality factor.� Work is currently underway to develop a transparent top contact to the nanowire arrays and optimize the doping level of the nanowire core and shell layers to improve the diode characteristics.�
