Silicon nanowire (SiNW) arrays are of interest for applications in photovoltaics and photoelectrochemistry.  High density SiNW arrays offer several potential advantages for solar cell applications in terms of processing costs, conversion efficiency and device stability.  The development of nanowire-based devices has been limited, however, due in part, to a lack of understanding of the basic electrical properties of SiNWs and nanowire array structures. 

Our studies in this area are therefore focused on fabricating and characterizing the electrical properties of high density SiNW arrays.  The nanowires are synthesized using a vapor-liquid-solid mechanism, in which gold serves as the catalyst for axial wire growth from a Si-containing precursor gas.  In the prior year of the program, we investigated the resistivity of SiNWs fabricated by VLS growth in metal-infiltrated nanoporous alumina membranes.  The alumina membranes provide a support structure for the aligned growth of nanowires and also enable the fabrication of electrical contacts via the top and bottom membrane surfaces. Our studies revealed, however, that the alumina membranes also introduce impurities, most likely aluminum, into the SiNWs during growth resulting in p-type conductivity with a nanowire resistivity on the order of 1 ohm-cm for “undoped” structures. This relatively high acceptor background is undesirable for photovoltaic applications.   

In order to further study the impact of the substrate on SiNW resistivity, we have focused our efforts during the past year on the fabrication and characterization of nanowire arrays grown on high purity Si substrates.  Epitaxially oriented SiNW arrays were fabricated on (111)Si substrates by VLS growth using SiCl₄ as the Si source gas.  Our nanowire array fabrication studies have focused on investigating the effect of growth conditions on wire orientation, structure and growth rate. Wire orientation was found to be strongly dependent on the growth temperature with ~ 80% of the SiNWs being <111> oriented perpendicular to the substrate at 900^oC but dropping to ~18% at 800^oC.  At low SiCl₄ partial pressures (P_SiCl4), the growth rate of the wires increases with increasing P_SiCl4 reaching a maximum of ~ 3 μm/min at P_SiCl4 of 3.7 Torr.  Beyond this point, the growth rate begins to decrease with increasing P_SiCl4.  Thermodynamic modeling studies revealed that the growth rate behavior arises due to a shift in gas phase equilibrium which promotes the reverse Si etching reaction at high SiCl₄ partial pressures.

The resistivity of nominally undoped SiNWs grown using SiCl₄ was studied using four-point measurements carried out on individual SiNWs released from the substrate by ultrasonic agitation and assembled onto pre-patterned back-gated test structures using field-assisted assembly. This work was carried out in collaboration with Prof. Theresa Mayer in the Electrical Engineering Department at Penn State.  Nominally undoped SiNWs grown on high resistivity (111)Si substrates (r=2,000-10,000 ohm-cm) were found to have a high room-temperature resistivity, on the order of 6,000 ohm-cm.  Assuming that the carrier mobility in the NWs is similar to that of bulk Si, this indicates a background doping level of <10¹⁴ cm^-3 for undoped SiNWs grown on high purity Si substrates. 

During the remaining period of the project, our studies will focus on intentional doping of the SiNWs grown by VLS on Si substrates and the fabrication and electrical characterization of axial and radial p-n junctions in the nanowires.